1. Field of the Invention
This invention relates to the field of complementary metal oxide silicon (CMOS) memory arrays and a means for biasing a well in which such memory arrays are formed.
2. Background Art
Memory arrays processed using CMOS technology often include memory cells formed in a well of a P or N conductivity type. It is often desired to bias this well to a voltage level above that of the supply voltage for N-well CMOS memory arrays, or below the power supply ground for P-well CMOS arrays. The well is biased in order to reduce leakage current (both isolation and access transistor) in the memory array cell.
In the past, a ring oscillator coupled to a substrate pump was utilized to provide biasing. A disadvantage of ring oscillators is the strong dependence of the output frequency on the supply voltage. The frequency of the ring oscillator is proportional to the square of the supply voltage. Thus, even small changes in supply voltage can create large shifts in output frequency. A second disadvantage of the previous method results from the use of a substrate pump. The substrate pump must supply, in addition to the injection and avalanche multiplication currents in the substrate, the leakage current of the memory array. These additional currents require large power consumption by the ring oscillator and charge pump.
In order to overcome the disadvantage of varying frequency, the prior art has provided a voltage regulated lower bias supply to the ring oscillator. Although this reduces power consumption of the oscillator and provides a more constant oscillating frequency source, the voltage regulator providing this regulated bias voltage supply dissipates the power drop to the oscillator as well as consuming additional power itself as needed to provide a constant regulated voltage.
Other attempts to reduce power consumption include duty cycling the ring oscillator when the pump node has reached its regulated voltage. In order to determine when to shut off the oscillator, prior art methods have utilized an inverter as a comparator having a trip point as a reference at approximately VCC/2. When the inverter is tripped, the oscillator is shut off, and does not draw power until the substrate node falls below the reference level voltage. This method has a further disadvantage of unacceptable process sensitivity.
Therefore, it is an object of the present invention to provide a means for supplying leakage currents to a memory array, particularly a CMOS memory array having low power consumption, frequency independence, and process insensitivity.
It is a further object of the present invention to provide a means for biasing a well of a memory array in which the frequency output is independent of the supply voltage.
It is a further object of the present invention to provide a means for biasing a well of a CMOS memory array in which the well voltage maintains a constant relationship to the supply voltage.